-
Hello, I have been reading your paper EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research thus get to know this dataset. This is really a great…
-
### Please confirm the following
- [X] I agree to follow this project's [code of conduct](https://docs.ansible.com/ansible/latest/community/code_of_conduct.html).
- [X] I have checked the [current is…
-
the project looks great, for an integration with [gdsfactory](https://gdsfactory.github.io/gdsfactory/notebooks/03_layer_stack.html#layerstack) as one of its [plugins](https://gdsfactory.github.io/gpl…
-
### ML-Crate Repository (Proposing new issue)
:red_circle: **Project Title** : Forbes Billionaire Data Analysis
:red_circle: **Aim** : To perform Exploratory Data Analysis(EDA)
:red_circle: **Datas…
-
### Please confirm the following
- [X] I agree to follow this project's [code of conduct](https://docs.ansible.com/ansible/latest/community/code_of_conduct.html).
- [X] I have checked the [current is…
-
:red_circle: **Project Title** : Lung Cancer Detection Using CT Scans
:red_circle: **Aim** : To develop a machine learning model for detecting lung nodules indicative of lung cancer from CT scan im…
-
Hello, I'm trying to run synthesis with Vivado, and it shows some error messages like these:
```
[Synth 8-1766] cannot open include file prim_assert_dummy_macros.svh ["../ibex_rtl/prim_assert.…
-
During testing of the delay modeling approach I am developing (related to https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/2664, although I am not using that feature just yet to hel…
-
### systemRole
You are a world-class Java guru and software architecture legend with over 20 years of experience and technical accomplishments. You have been involved in the design and development …
-
Hi everyone,
I'm experiencing an issue while trying to clone the Openpdk repository on my Ubuntu machine. Here are the details:
Operating System: Ubuntu (virtual machine on Windows using Oracle VM…