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**Type of issue**: bug report
**Impact**: no functional change
**Development Phase**: request
**Other information**
**If the current behavior is a bug, please provide the step…
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I'm trying to create a reg vector which will be initialized to zeros, but running into uninitialized errors. Based on the cookbook I wrote the code below:
```
val zeroComplex = DspComplex(Real[T].…
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### Checklist
- [x] Did you specify the current behavior?
- [x] Did you specify the expected behavior?
- [x] Did you provide a code example showing the problem?
- [x] Did you describe your envir…
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### Checklist
- [x] Did you specify the current behavior?
- [x] Did you specify the expected behavior?
- [x] Did you provide a code example showing the problem?
- [x] Did you describe your envir…
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**Type of issue**: feature request
**What is the use case for changing the behavior?**
Clock gating currently requires external blackboxes that contain synthesizable clock gating constructs (e…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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When I write a FIRRTL program like this:
```
circuit FormalSimple :
module FormalSimple :
input clock : Clock
input reset1 : UInt
output io : UInt
wire a1 : UInt
wire a…
wky17 updated
2 months ago
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The original iteration of this bug was fixed in https://github.com/llvm/circt/pull/6912, but it appears that fix only works for registers in modules contain the wire or port marked with a `circt.FullR…
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FIRRTL memories that do not go through the `--repl-seq-mem` path to replace them with blackboxes always produce a wrapper module around the memory. However, this can result in poorer performance for V…
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When I use CIRCT to compile, I got these erri
```
Running CIRCT: 'firtool -format=fir -warn-on-unprocessed-annotations -verify-each=false -dedup -annotation-file build/SimTop.anno.json < $input'
--…