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hello !
I meet a problem like this when i run test_program_rpc.py.
xiaoliyang@xiaoliyang-virtual-machine:~/tvm$ python3 vta/tests/python/pynq/test_program_rpc.py
Traceback (most recent call last…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Ok so basically, I need to use CVA6 to add a peripheral to it. For that I want to open …
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Might it be a good idea to offer one of Xilinx' smaller FPGAs in the SNAP config menu, which could only be used for simulation but doesn't require a paid Vivado License?
As I was scrolling through …
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Hi, thanks for the good work!
Maybe I missed something, but I couldn't find an example of how to initialize a register value:
```veryl
pub module RegisterFile (
i_clk: input clock,
) {
v…
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I'm not sure exactly where on the wiki to start this conversation, but I'm here compiling a few links on LabVIEW FPGA compilation. It's a relatively mature ecosystem that National Instruments has crea…
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The Xilinx XC9500XL series is a popular CPLD series. It's 5V-tolerance, relatively low price, and many I/O pins make it a good choice for many projects.
IMO, this would be a good candiate for a new…
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Hi，
I follow https://github.com/JunningWu/Learning-NVDLA-Notes/wiki/7-FPGA-Based-on-Xilinx-ZCU104
1. where to download this 交叉编译器? it's a xilinx gcc?
3x a lot.
Kou
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Hi,
I am one of the early purchasers for your Mercury 1 board and have contacted you a couple of years back regarding Linux support for Mercury board. I am glad that there is Linux support now for yo…
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https://blog.kevinly.com.cn/2023%E5%B9%B4%E7%94%B5%E8%B5%9BH%E9%A2%98-%E4%BF%A1%E5%8F%B7%E5%88%86%E7%A6%BB%E8%A3%85%E7%BD%AE-%E5%B0%8F%E8%AE%BA/#more
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After set Verdi ourself, we will generate netlist of Altera/Xilinx with synplify, is there any Altera/Xilinx RAM for replace, or it must be generated by ourself.
We plan to generate 2 netlist, whic…