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Hi,
I was wondering how you chose arty_a7 for the sample projects? Why you didn't choose the zen board?
Thanks
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The harness should be changed to present N 'axi-like' ports. Then, different memory access patterns (& multiple memory ports) can be implemented inside rigel (& will behave the same in hardware and th…
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Hi all
I tried to run the dhyrstone test on Pulpino RISCY Core by adding source code (dhrystone.c dhrystone.h dhrystone_main.c encoding.h /*from env folder*/ util.h) and used cmake to add this …
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There is a few attempts to works with Xilinx SOCs with Hard ARM cores. I find these examples difficult to follow.
The example below is what i tried, and finally worked.
The principle is this: add …
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Dear Nikkatsa.
In your work, I just want to understand video path from usb webcam to VGA display. For my learning, it would be easy for me if you provide/guide your project without HOG implementati…
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I am getting the following warnings after cloning branch 2020.1 of hdf and petalinux and master for bdf
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_bram_ctr…
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Hi, I am trying to use the kernel and the roots on the SD card. I get the system booted, but have a problem with the arm login. Could you provide the user name and the password so that I can actually …
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- Also this one empty newline is not needed
For imxrt117x this log is not …
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Hi Jamey,
In case of memcpy, the program finishes with status 0 (successfully) unlike previously with older images. But when I print the src and dst array in software's **done** function, some of th…
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In the datapath, there is DMA setup time modeling, which delays the DMA transaction considering CPU cache flush or invalidation latency. However, to my knowledge, directory controller of MESI_Two_Leve…