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The SymbiFlow project is centered around the support for various FPGA technologies. Many projects that constitute SymbiFlow are not directly related to hardware, however they still might require some …
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I have followed the instructions in the readme so far but when it comes to loading the bitstream to the Arty A7-100 I get errors.
When I run `./make.py --board=arty --load` i get this error:
`Tr…
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The following Vexriscv configuration hangs when you try to run on the board:
`generate+bypass:false+csrPluginConfig:mcycle+dCacheSize:0+hardwareDiv:false+iCacheSize:8192+mulDiv:false+prediction:non…
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It would be great for the Yosys version in YoWASP to have better SystemVerilog support through the usage of the Surelog+UHDM plugin. What would be the steps for making such a thing happen? Do plugins …
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**Description**
Dumping the signals in the below unit with `--wave` causes the unit to abort with the following backtrace:
```
#0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/rai…
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After starting a clean install with
git clone https://github.com/QuickLogic-Corp/qorc-sdk.git
cd qorc-sdk
source envsetup.sh
the installer finishes the process, but bitstream is not generated …
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Hello, why don't you use instead of the commercial and closed Vivado, its open counterparts, such as gEDA, icarus verilog, kiCAD ...
The fact is that the cost of a license for Vivado is very expens…
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at the merge of the high performance banks https://github.com/f4pga/prjxray/actions/runs/3534822169
a number of lines from the fuzzer 034b-cmt-mmcm-pips disappeared from these database files:
```d…
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All toolchains classes have more or less the same structure / logic with most of the logic residing into `build` method.
It may summarise by:
1. directories creation
2. finalize the design
3. veri…
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I would like to ask what is the state of support for SV union with the git versions of the plugin and yosys.
For now I can see there is no outright error stating unions are not supported as was there…
jeras updated
2 years ago