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For simplicity, let's use the standalone generator:
```
$ ./gen.py arty.yml
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> < …
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**Describe the bug**
A clear and concise description of what the bug is.
After building the firmware and flashing it on to the hardware, the Zephyr RTOS boots as expected. But while running telnet …
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## Branch / Commit Hash
top_dev: af8beff
## Area
bp_me_axil_master module
https://github.com/black-parrot/black-parrot/blob/top_dev/bp_me/src/v/network/bp_me_axil_master.sv#L113
## Current …
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From my studying of the source code so far there does not appear to be support for any wired ethernet adapters right now, as all networking examples and capsules presume the usage 6LoWPAN wireless net…
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- [x] Use 32-bit datapath for the IP/UDP Stack + Etherbone (will be posssible with current work in https://github.com/enjoy-digital/liteeth/pull/21).
- [x] Reduce `sys_clk_freq`.
- [x] Integrate SDR…
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The signals are probably simplified during synthesis, and missing when applying the constraint:
````
ERROR:ConstraintSystem:59 - Constraint [top.ucf(80)]: NET "eth_rx_clk" not found. Please veri…
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### The issue
It appears that when LiteX switched from 8-bit CSR bus to 32-bit CSR bus, the Zephyr drivers were not updated.
The riscv_litex Zephyr port is not really operable in this situation, as…
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Hello,
I'm having a problem with etherbone: the connection stops working if two packets are sent too close to each other.
The only way to restore connection is to power cycle the board.
The packets…
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Hello,
I'm trying with Altera DE2-115 kit. I have added ethernet patch to make TFTP boot work. However, the booting is hang at step `Freeing unused kernel image (initmem) memory: 2708K`
For the dts …
lapnd updated
2 years ago
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Because of this filtering by target IP https://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/ip.py#L212 LiteEth devices do not receive broadcast packets - ones sent to .255 etc addresses.
…