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I'm running through the README.md in the soc/software/demo folder. I'm able to build the bitstream and compile demo.bin. But litex_term is hanging when I run:
```
litex_term /dev/ttyUSB1 --kernel=de…
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I successfully downloaded the kernel (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/164) to kcu105 using tftp, but I don't see eth0 after using ifconfig -a, only Io and sit0 exist.
![im…
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**Describe the bug**
k_busy_wait() never returns when called.
Hardware details
Board - Xilinx AC701
SoC - Litex
CPU - Vexriscv
**To Reproduce**
Steps to reproduce the behavior:
1) Build li…
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**Note on Bugs**
I am running bmc image (details below) and trying to access the sd card attached to the board. However when i type in fdisk -l , it shows nothing. If i look into the dmesg, i see not…
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How hard would it be able to get this project running on VC707 boards?
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**Describe the bug**
Calling k_msleep never returns on litex_vexriscv hardware using colorlighti5 Lattice board.
**To Reproduce**
Steps to reproduce the behavior:
1. Modify samples/HelloWorld/ma…
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## Background
I am trying to simulate my own SoC design based on the default litex_sim, aka I only added a couple of custom modules, everything else should be the same, so I can also test this issu…
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hello, i've been working through the labs and i've encountered an error on lab004 that i'm not quite sure how to fix. when running the commands in step 2, i get the following error:
```
$ make all…
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**Describe the bug**
A clear and concise description of what the bug is.
I'm looking for help with Litex Vexriscv on an Arty A7 35T. I'm unable to boot zephyr no matter what I try and I'm wonderin…
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https://github.com/enjoy-digital/liteeth/blob/435c67dbc774ab2f49c6d53f5f63417ba4af7605/liteeth/frontend/stream.py#L25
src_port, dst_port, and ip_address need to be hooked up like they are in the fi…