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There is good microelectronics group at my depatment. They saw our activities and asked if we need some ASIC development. They have some founding, tools and production possibilities. They have also [b…
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*Edit by @dmerejkowsky, so that the task list appears in the issue*:
Guides to write:
* [x] Creating a basic manifest repo, using `init` and `sync`
* [x] Editing `.tsrc/manifest.yml`
* [x] Usin…
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Solicit suggestions for agenda items for the Governance meeting to be held on Tuesday July 18 @ 15:00 UTC in grincoin#general channel on [Keybase](https://keybase.io/team/grincoin#general). Please com…
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3.4.0 lists rst_i as a required signal for masters and slaves. In practice, the rst_i signal should not always be needed. Even the example in A.7.2 does not include rst_i
(discovered by Alfred M. S…
olofk updated
3 years ago
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### Description
After hardening a design with openlane:
`./flow.tcl -design spm`
I try to open the gui (which worked about a month ago):
`./flow.tcl -design spm -tag RUN_2023.04.26_09.09.28 …
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[ERROR] [input_files.py:370] filter has no residues/poles, cannot save txt file
can you tell me why ?
or can you give me a txt file can be loaded by pyfda?
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#### Description
When the testcase sflow/test_sflow.py::TestReboot::testWarmreboot was run, it fails because no sflow samples were received after warmboot.
#### Root cause:
Host sflow deamo…
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http://covered.sourceforge.net/
http://www.asic-world.com/examples/systemverilog/index.html
https://github.com/FPGAwars/FPGA-peripherals/wiki/Asynchronous-serial-receiver-unit
https://verificationa…
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Hi all,
After a looong time spent on ironing-out some issues, I finally have a working PULPissimo based SoC with 5 hardware accelerators. I've implemented a few applications so far with the design,…
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@cliffordwolf @FSMaxB @gordon-quad
We need more examples, what do you all think we need to add? (hoping we could brainstorm, I also have some time this weekend to create stuff)
Some ideas:
- C->Ver…