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Observed with the Arty A7-35T board. It seems that `mem_2` is the storage for SoC CSRs.
Each time I run `litex_boards/targets/digilent_arty.py`, a few bytes towards the end of `mem_2.init` cha…
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Hi, I am trying to implement SPI interface. I am referring the provided example /freedom-e-sdk/software/example-spi. I am trying to validate if my transfer is successfully completed or not. Does anyon…
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I have purchased 5 of the QMTech boards for work purposes (arriving later this week), so should be able to use one to experiment with the open source flow. I also have (limited) access to the Genesy…
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While I was working on #976 and #988 I noticed that femtorv has some issues with memory when booted on board.
Seems like it isn't my fault, as it also happens on master branch.
Steps:
1. `pytho…
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Hi all,
Apologies if this is the wrong place to ask, but I'm having issues getting my bit file into the ARTY 100 board loaded. Here's what I did so far:
- Installed Symbiflow and all its depende…
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I use the Murax scripts and follow the instructions to the word, i.e.
modify `src/main/c/murax/hello_world/src/main.c`
`make`
`make prog`
`make flash`
`press the PROG button`
Where could I be …
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Reported by @gsomlo: https://libera.irclog.whitequark.org/litex/2021-09-27#30904583
cc @kgugala, @michalsieron.
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It would be useful to have a way of generating the names of boards potentially supported by CFU-Playground. The simplest implementation would just list the boards in `litex_boards/targets/`. It's …
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https://github.com/litex-hub/litespi/blob/master/litespi/core/mmap.py#L106
When used in https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/digilent_arty.py, litespi has a 10…
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# Description
According to the comment in source file, the latest update of this project is in 2014. However, 5 years later the ARTYA7-100T REV.E has come to market. The error is the serial output t…