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From
``` scala
class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
val data = Bits(width = coreInstBits)
val datablock = Bits(width = rowBits)
}
```
As f…
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I try to use the `MegaBOOMConfig` in the `boom` branch of the `rocket-chip` repo, but it fails at the following requirement in `rocket/frontend.scala:126`
```
require(fetchWidth * coreInstBytes
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https://docs.google.com/spreadsheets/d/1Tp0p0TXWaR0-l9x9-KPdCb-kJDgelJKXZD5nAzbrM_A/edit#gid=0
But not all I think (because of OP-ness, excessive accumulation etc.)
List (ticked means, that it could s…
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I got bitten by this today. If you are using a RoCC accelerator, you need to remember to tie io.mem.invalidate_lr to false or else LR/SC instructions will continuously fail.
Since this keeps happenin…
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Gathered from the forum.
- So the Harappan Reservoir doesn't give Lake Tiles +1 Food unlike the Aqueduct.
- Because of the -20% RCS from Logistics, the Ship of the Line now has a lower RCS than Gallea…
Edaka updated
8 years ago
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Hwacha makes use of zero width wires and I would prefer not to add lots of workarounds for a feature that will be eventually added.
Is there an ETA for this support?
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_1. Mod version:_
10/12, not the Multiplayer version. With EUI.
_2. Mod list (if using Vox Populi only, leave blank):_
_3. Error description:_
exactly the same as issues #1944 and #2236. Both are c…
ghost updated
8 years ago
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Chisel 3 runtime is about 9-10 minutes for this configuration of Hwacha to generate FIRRTL. Chisel 2 creates verilog for this config in 3 minutes.
Chisel3 Output
```
[info] Running rocketchip.TestGe…
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A read from a non-power of two memory can be initialized with an address that is out of the range of the memory. In vcs this results in an X output, potentially propagating throughout the rest of your…
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After manually installed tweepy (#8). I just ran py.test and tried to see what was happening. There were just 3 tests and all of them failed with something like this.
```
Traceback (most recent call …