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## Problematic test case
```systemverilog
module test #(
parameter int BobaCount = 2,
parameter int unsigned NumBobaDrinkers[BobaCount] = '{default: '1}
)();
endmodule
```
UHDM:
```
…
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The final installation command is very easy to mess up.
`for PKG in $F4PGA_PACKAGES; do
wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-d…
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Repro case:
```systemverilog
typedef struct packed {
logic a;
logic b;
} status_t;
module advanced (
output status_t status_out00,
output status_t status_out01,
output sta…
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Each individual notebook needs
-Explanations
-Diagrams if applicable
-Practice questions
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Putting the following example in the flow SV --> UHDM (w Surelog) --> Yosys (w f4pga plugin) --> SV shows that the following verilog with bit direction is incorrect:
Input:
```systemverilog
modul…
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We need to update the documentation for Symbiflow to reflect its new name (f4pga).
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Reading the following verilog with UHDM then Yosys-f4pga results in the wrong values:
```
module static_size_casting (
output wire [ 7:0] out1,
output wire [ 7:0] out2,
output wire …
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Hi everybody, I am using a recent updated Fedora 38, I was compiling this project in Fedora 36 without issues, but now I get this error:
![compilation_error](https://github.com/f4pga/prjxray/assets/6…
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from https://github.com/chipsalliance/Surelog/issues/3375
Reading this Verilog with UHDM then Yosys has the wrong values.
```
typedef struct packed {logic [3:0] a;} my_struct_packed_t;
modul…
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Related to: https://github.com/chipsalliance/yosys-f4pga-plugins/issues/503
TEST:
```
package foo_flags;
typedef struct packed {
logic a;
logic b;
logic c;
} common_flags_t;
e…