-
I try to build system based on vexriscv, build I/D subsystem like below:
```
val core = new ClockingArea(coreDomain) {
val vexRiscVConfig = VexRiscvConfig(plugins = vexRiscVPlugins)
…
-
```
Guru Meditation Error: Core 1 panic'ed (Interrupt wdt timeout on CPU1)
Core 1 register dump:
PC : 0x400813eb PS : 0x00050234 A0 : 0x4008489c A1 : 0x3ffbe7b0
A2 :…
-
Hello , sorry for asking for improvement via issue
is there any plan to add deep sleep functionality and time fetch from NTP (to keep time up-to-date) ? for making it battery friendly project
i…
-
https://github.com/khoih-prog/TimerInterrupt
-
- #### Context
I am writing an 88-2SIO device for the AltairZ80 simulator and have run into a problem with the multiplexer with an attached serial port that I cannot figure out.
The CP/M ba…
-
Have some proposed changes I'd like some feedback on.
A new tag to add metadata to components:
```
case class ComponentMetaTag (
displayName : String = null,
author …
-
### Version/revision of the library used
v2.6.3
### Actual behavior
When I use the bare library, everything works as expected. But as soon, as I activate some hardware-based PWM on a completely o…
-
This issue is to open discussion around Timer management in order to provide useful API.
Current implementation is limited to support basic Arduino function.
Any help/comment are welcome.
-
My intention with creating this issue is collecting/sharing information and gauging interest about running Linux on VecRiscv. From what I know, VexRiscv is still missing functionality, and it won't wo…
ghost updated
5 years ago
-
Hi,
After compiling the VexRiscvAvalonForSim example, I imported the TCL component into Quartus but trying to instantiate it inside Platform Designer I receive the following errors:
```
Error: …