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Hi,
my goal is to eventually run a configurable nv_small on Zynq Ultrascale+ while using an nvdc compiled caffe model for inference. I am still a novice in the field of FPGAs, NNs, etc. and have some…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?
Thank you and congratulations on your project.
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Hello,
I'm trying implement this on Zynq Ultrascale with directly connecting to AXI buses.
Do it need additional changes in design to accept such connection?
Did you tried such implementation ?
…
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Hi.
I don't want PTW in my Rocket SoC because I am not using Virtual Memory. I have tried to remove it class from the Tile.scala but I am getting the compiler error.
Can someone help how can I r…
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I am currently trying to create a hwpe datamover that transforms the hwpe interface into axi4 streams such that i can use different existing ips directly with PULPissimo. This work is part of an unive…
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I modified the testbench to demonstrate at line 209 as follows
``ifdef TB_VERBOSE
$display("test read");
`endif
```
ready
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Hi @ztachip, have you, for the sake of performance and simplicity, considered replacing 2-cycle APB with a generic VALID/READY interface?!
That latter can perform transaction in a single-cycle, an…
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Hi,
I would like to add Wishbone protocol support to Constellation. However, the documentation is confusing me. Furthermore, due to the changes made to Chipyard (refer to #41), it is challenging to…
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From the vhdmmio general documentation:
> vhdmmio concerns itself with the generation of register files. To vhdmmio, a register file is an AXI4-lite slave, consisting of any number of fields, occup…
m-kru updated
3 months ago