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When I try to use "pip install fault", I get this error,
ERROR: Command errored out with exit status 1:
command: 'E:\Anaconda\python.exe' -c 'import sys, setuptools, tokenize; sys.argv[0] = …
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```
test_simple_alu.py .......F [100%]
=================================== FAILURES ===================================
_________________ test_simple_…
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What problems am I trying to solve?
-Better and safer mechanism for utilizing external libraries in coreir
-Ability to define and create multiple library implementations for coreir libraries.
-Link…
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There are 3 main mantle targets:
-- boards (ice40, altera, etc.)
-- CoreIR
-- Verilog (not heavily used)
There are 3 main compilation outputs:
-- Verilog
-- CoreIR
-- CoreIR-Verilog
I beli…
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The test https://github.com/David-Durst/embeddedHaskellAetherling/blob/2afef5715c0109e2b212656f890426bfe169bfac/test/Test_Slowdown.hs#L484-L485 is extremely slow.
```
λ: :set +s
λ: stencil_1d_res…
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Currently the `CE` signal is wired to the tile-level clock-enable signal. Ideally this should be wired to a signal that ands the clock-enable signal and the register mode signal. In other words, we sh…
Kuree updated
5 years ago
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I'm having trouble while compiling GarnetFlow repo at https://github.com/StanfordAHA/GarnetFlow. The error is like:
`In file included from /GarnetFlow/scripts/coreir/src/../include/coreir/ir/common…
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Hi all,
Does anyone know how can I solve the errors in this compilation?
Thanks a lot in advance
I quote, "/Users/fengshi/Workspace/coreir/src/../include/coreir/ir/json.h:1636:11: **error**: '**…
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- [ ] `coreir.udiv`
- [ ] `coreir.urem`
- [ ] `coreir.sdiv`
- [ ] `coreir.srem`
- [ ] `coreir.smod`
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My [travis build fails](https://travis-ci.com/David-Durst/aetherling/builds/111998863#L3397-L3496) because CoreIR's json to verilog compiler causes the VM to run out of memory on https://github.com/Da…