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### Description
Hello! While writing a custom step I'm facing the challenge to inject custom Verilog into the flow.
By this I mean the ability to add new files to the `VERILOG_FILES` variable. Unf…
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Hi,
I was thinking whether it would make sense to check the sorting network proposals generated by the evolutionary algorithm using an FPGA. I will try to explain what can be done on an FPGA and ho…
jeras updated
1 month ago
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If one writes `nameHint (SSym @"hi") ...` there is a good chance that GHC's `unpack` rewrite rule will rewrite the `String` in the term-level evidence carried by `SSym` (which is the only thing preser…
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> ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [../../../../../../../riffa_hdl/functions.vh:44]
ERROR: [VRFC 10-1342] root scope declaration is not allowed in ver…
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How can I synthesize this using Quartus Prime ( windows). I have tried Adding the project and Running the files , but all i get are analysis error
Note : files are added as it is in project.
for E…
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Hi all, I'm trying to simulate the project for VC707 (VC707_gen1x8lf64) using Vivado 2015.4. The Vivado runs on Ubuntu 14.04. However, the simulation has errors as following:
ERROR: [VRFC 10-1342] …
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Would it be possible to have rust-hdl output to circt. https://circt.llvm.org/
One could then use the LLVM/MLIR to optimize the output before outputting System Verilog or VHDL.
For example rust is …
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Hi! I am trying to compile the project for a De0-nano board following the instructions. Nevertheless, quartus can't compile the project, here is the messages that I get:
Info (12128): Elaborating e…
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Hi! I really like the project and would see a ton of use for it in our FPGA/ASIC projects. However, one blocker I see is the lack of parameters on the HDL modules generated. I often have multiple inst…