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How to use gf180mcu-pdk into openlane flow?
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the following [line ](https://github.com/efabless/caravel-gf180mcu/blob/main/verilog/rtl/chip_io.v#L349) in chip io triggers the following syntax error
```
genvar i;
generate
for (i…
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There are net mismatches in the nets on the SRAM interface in the abstract LVS.
I reviewed some of them and the layout was correct.
This might be a problem with the extraction from LEF, not the lay…
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the included `lef` for `user_proj_example` is for sky130, so running `make harden` which happens to build `user_project_wrapper` first using the old lef results in the following error:
```
[ERROR]…
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## Expected Behavior
`simple_por` DRC clean
## Actual Behavior
`simple_por` has a violation in rule `LPW.2a_5V_`
## Steps to Reproduce the Problem
1. build the pdk
2. run `python3 run_drc.…
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As discussed in https://github.com/efabless/volare/pull/20#issuecomment-1241737557 we need to modify the CI workflow to publish volare build of gf180mcu.
This depends on https://github.com/efabless…
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Hi @klayoutmatthias ,
I'm still working on investigating the performance issues in DRC that we are facing. I ran another profiling to see where is the main issue:
```
2022-11-22 21:36:11 +0200: M…
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all views of sram wrapper should be in the repo
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### Description
Running `-synth_explore` using the docker image (2023.01.03) can result in a `TypeError: 'NoneType' object is not subscriptable` error. The `analyze.py` file fails when trying to anal…