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The user_project_wrapper has `vdd` and `vss` pins on the left side that are treated as data pins. Both pins should be eliminated.
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### Description
I am currently trying to reharden a design for submission to GFMPW-0. While this previously worked well, now I get a crash during Global Routing Resizer Timing Optimizations. The de…
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### Description
When integrating several hardened macros into `caravel` then the `m4` vertical PDN straps run through some of the macros.
### Expected Behavior
The `m4` straps are cut where there i…
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I need a straightforward mapping of layer names to GDS types/subtypes. I believe this information is captured by various tool configuration files, like `gf180mcu.lyp` for klayout, but it would be help…
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Can anyone tell help to change the pdk from sky130 to gf180mcu??
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```
chip_io padframe(
// Package Pins
`ifdef USE_POWER_PINS
.VDD (VDD), // Common padframe/ESD supply
.VSS (VSS), // Common digital ground
…
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## Expected Behavior
Do not corrupt connectivity (leading to false or dropped errors) by using layers that are not part of the fab process.
Do not read/merge/count data from such superfluous layers.…