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https://github.com/SymbioticEDA/riscv-formal is a framework for formal verification of RISC-V processors which uses fully open source tooling.
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Hello Stephan,
I hope you are well.
I managed to build the blink_led example on Segger's EmbeddeStudio, however when I upload it to NEORV32 via UART I receive error_0 which is related to the execu…
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```
# ecppack
Mingw-w64 runtime failure:
32 bit pseudo relocation at 00007FF784896911 out of range, targeting 00007FFAB975DA10, yielding the value 0000000334EC70FB.
```
That is producing failur…
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Hi,
as the NEORV32 supports gernerically the iCE40upK5 and other FPGAs it would be great to have a template for adding a new, currently not supported board. So adding support for all the baord arro…
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I installed asciidoctor and ruby-asciidoctor-pdf in Ubuntu 20.04 (WSL).
Then it complained about asciidoctor-diagram.
Then I installed it using a gem install asciidoctor-diagram
Then when I type…
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Hello,
it looks that the size information for the SYSINFO section is wrong, 0x1F.
Compared to GPIO which have a size of 0x10, I think SYSINFO must be 0x20.
Best regards,
Michael
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To keep people from accidentally committing the HTML report to git, or to keep them from having to edit their .gitignore to prevent it, the html command can write a .gitignore file into the directory.…
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Moin Stephan,
nice to meet you again in RISC-V territories!
We were busy on the Verilog side, too:
https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV/RTL/PROCESSOR
But while tacklin…
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Coming from #98.
> https://github.com/stnolting/neorv32/pull/98#issuecomment-874138098
>
> The OrangeCrab has an external DDR with 128 MB. Hence, the mid-term goal should be to append a controlle…
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In the osflow setup, the guide is out of date. The first step is to run `make`, but this generates an error because the makefiles do not set `TOP`, `BOARD_SRC` and `DESIGN_SRC`.
I am referring to t…