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**Describe the bug**
The user guide chapter 1.3. installation has a wrong export statement for the PATH variable.
**To Reproduce**
```{bash}
$ export PATH:$PATH:/opt/riscv/bin
bash: export: `PA…
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I tried to implement the neorv32 core to a cyclone II device EP2C8Q208C8. The tool I use is Quartus II 13.0 64-bit.
I followed the well documented user guide step by step to build a simple project. B…
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I have an Altera DE2 with Cyclone II dev board which was bought more than 10 years ago. Does Neorv32 support it ?
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**Description**
The GHDL (+yosys) based implementation workflow of the [NEORV32](https://github.com/stnolting/neorv32) master branch fails since ~7 hour ago.
**How to reproduce?**
All implementat…
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**Describe the bug**
Building the project fails at the last step ("Export Files"), all prior steps work.
The build output:
```
************************************************************
*…
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Currently, all tasks of the implementation workflow (triggered by PRs) keep failing with the following error message:
```
synth_name: cannot handle IIR_KIND_SELECTED_ELEMENT (../../rtl/core/neorv3…
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Dear author(s),
I have been trying to synthesize the top CPU module of the NEORV32 core using custom cell libraries. However, yosys cant seem to find the cpu entity which has already been analysed.…
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I started a new design today and Vivado won't let me insert the neorv32_SystemTop_axi4lite-template into a block design.
I could track the issue down to the new TRNG-Module: when **not** enabled th…
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In "neorv32/docs/userguide/content.adoc"
The command `./configure --prefix=/opt/riscv --with-arch=rv32i –-with-abi=ilp32`
it shoudl be `./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi…
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Hello,
Can this core be able to run Linux on it?