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I'm using two dma in my design
my system-user.dtsi in petalinux is like this
my pl.dt…
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Hi all,
I am following the steps described in https://libvirt.org/kbase/launch_security_sev.html to enable SEV in the kernel of my AMD Ryzen 5 PRO 2400G (with Ubuntu 18.10). However, for some reas…
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Issues are for bugs in syzkaller itself, for everything else please contact syzkaller@googlegroups.com mailing list.
Before filing an issue please check the existing issues and the mailing list (ht…
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## Objective
- To make VTA available for intel FPGA.
- To demonstrate the quantized resnet18 on DE10-nano.
## Interface Changes
- `tvm/vta/hardware/intel_fpga` would be created.
- Interface…
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Hi Brandon,
I'm trying to use your driver on a zedboard but the error in the title comes up, I tried increasing to cma=45M in the hope that it would fix the issue but it doesn't.
After booting, …
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Hello,
I rune muse 2.1.2-3, on Debian stretch. https://packages.debian.org/en/stretch/muse
When I start muse I get a message about the timer that is 250Hz while it must be 500Hz.
Muse fallba…
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https://github.com/bespoke-silicon-group/bsg_f1/blob/be0d7b91ebc6028e9e5ba0f7f8b653f4e9ab486d/hdl/axil_to_mcl.v#L1
A description of what this is. Why is there a crossbar? Is it a single link or mul…
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I have a block design with AXI_DMA IP included, and I have verify it with bare metal system. Then I follow the README to build the driver/device tree/app. The "axidma.ko" can be inserted successfully,…
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Sometimes, when try to use two way transfer I get timeout error (in receive part). Also, I see that data correctly send out from DMA, but in some causes incorrect received (if set false on wait).
[t…
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Can your driver be attached to and run multiple DMA IPs (concurrently or one at a time)? If not do you have any plans to extend the driver to support multiple DMAs?