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Hello,
I have already integrated NVDLA small and tested on VC707, it works perfect. Now I want to try NVDLA large. It seems one can not integrate NVDLA large by using the guide https://www.esp.cs.col…
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The purpose of this issue is to ask the community what alternative naming to master/slave can be used in this repo and in other libraries projects related to VHDL. There have been multiple proposals, …
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Trying to migrate my hobby project SoC from VexRiscv to VexiiRiscv. I suspect there is a bug in FetchL1Plugic:
After fetching first few commands FetchL1Plugin produces unknown (`'xxxx`) output if c…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
Hi guys,
I am new to Rocket Chip and I could install the repo witho…
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Hello,
I was working on similar project.
My problem was that Vivado has too slow start and it was much more effective if it was running as a backend server and the client was sending the jobs fo…
Nic30 updated
5 years ago
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I have the axis_stream_fifo setup.
I attempt to read the data and display it in ascii.
I can read some data which should be a counter that I am clocking in, but all I get are zeros and then I get …
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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I stumbled upon an interesting bug. Linux is unable to boot if the memory size is above 512mb. In litex BIOS the whole ram passes the tests and its working but as linux start to boot it cant boot if I…
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I want to add a new slave peripheral to Riscv, and I took SRAM as reference to know the modules and packages that I should modify, and I found that I should add:-
1) Index, start and end address in t…
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Passing the following code to `--lower-std-to-handshake` produces a weird output.
```mlir
func.func @external_mem(%mem : memref) {
return
}
func.func @normal_mem() {
%mem = memref.alloc(…