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When I try to run OpenCache on the default config files, I'm getting this error:
```
nachiket in generator git:(dev*) 24-03-14 11:56AM python3 opencache.py tests/configs/config.py
|==============…
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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In Verilog, you can create an array like this: `reg[31:0] my_array[1023:0]`. You can then directly read from or write to the array. The array can also be synthesized as BRAM if you don't access it inc…
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Hello.
I want to get my feet wet with FPGAs via Amaranth-HDL. The toolchain needs `NEXTPNR_HIMBAECHEL`.
I get this error on the `make -j$(nproc)` step all the time. I have installed `apicula` vi…
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**BBB:**
debian@beaglebone:~/ldgraphy/device-tree$ sudo ./start-devicetree-overlay.sh LDGraphy.dts
make: 'LDGraphy-00A0.dtbo' is up to date.
Adding LDGraphy overlay
./start-devicetree-overlay.…
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code version: a87888ea72f806f05660aa1a4dd336fc5d80a6f2
```
Traceback (most recent call last):
File "/home/oleks/projects/orbtrace/./orbtrace_builder.py", line 112, in
main()
File "/hom…
retif updated
4 months ago
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To reproduce:
```python
>>> from amaranth import *
>>> from amaranth.lib import data
>>> Signal(data.ArrayLayout(5, 2))[-1]
Traceback (most recent call last):
File "", line 1, in
File ".…
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The current constraint format for GateMate chips requires the declaration of pin directions both in the constraint file and the HDL file such as `Pin_in`, `Pin_out`, `Pin_inout`. This approach is unco…
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In part 05, `with m.FSM` is used, and `fsm.state` is used within the with block. However, this causes an error which states that FSM doesn't have a property `state`. If you try to access `fsm.state` *…
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I propose:
- [x] documenting the complete set of names under `amaranth.hdl` that are provided for use by Amaranth programmers #785
- [x] making all of the existing modules under `amaranth.hdl` priv…