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git info: I am working on a fork of "dev" as usual.
I am trying to run some of the CGRAMapper examples through the simulator and before I can do that I need to add a clock to the inputs and wire up…
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Let's start releasing coreir. This should speed up any dependent Travis build by enabling them to download a compiled binary instead of having to build from source (except for any branches that tracki…
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Specifically create a shared library module for coreir-c.so which does not need to include coreir.so
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This branch changed "Param" to be a real C++ object called ValueType. I suspect the API will need to be updated accordingly. I also am using Dillon's dynamic_bit_vector class in order to do sized ints…
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```
coreir -p wireclocks-coreir -i popcount8.json
ERROR: Cannot select From self
Type: {'in1':Bit, 'out':BitIn, 'in2':Bit, 'in0':Bit}
Assertion failed: (type->canSel(selStr)), function sel, f…
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@dillonhuff Looks like it's failing because `mux` is the only 3-input operation supported. the `add` primitiver has optional `cin` and `cout` ports that will change the type signature.
```
❯ ~/rep…
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For example a magma->coreir compiled counter looks like the following:
```
{"top":"global.Counter4_flattened",
"namespaces":{
"global":{
"modules":{
"Counter4_flattened":{
…
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I am seeing a failing test when installing magma from scratch. I think it has to do with pycoreir not being a dependency
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coreir -i harris.json --load_libs lib/libcoreir-commonlib.dylib -p rungenerators,liftclockports-coreir,wireclocks-coreir -o harris.v
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This will look similar to the script we have for generating verilog modules.
I think this would be nice so that we could leverage it in the firrtl backends for both magma and coreir.
What do you th…