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This is an improvement request to add a DC remover block in the FPGA (just like it is done in Ettus USRP2) to avoid wasting CPU computation on that and thus resulting in a much cleaner signal.
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Author Name: **Clifford Wolf** (@cliffordwolf)
Original Redmine Issue: 730 from https://www.veripool.org
Original Date: 2014-04-03
Original Assignee: Wilson Snyder (@wsnyder)
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The following…
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As I was working through your code for this, I noticed the way the LSBs for the accelerometer data were being decoded looked strange (This bug applies to the decoding of all three axes, X being used a…
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Hi!
I'm admittedly new to Node.js and Postgres, so perhaps there is an environment issue that I am simply unaware of. Further, I'm a stranger to the project and am not sure if this is the appropriate…