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What's the difference between,
mpv-x86_64-20241112-git-43d8966.7z
mpv-x86_64-gcc-20241112-git-43d8966.7z
mpv-x86_64-v3-20241112-git-43d8966.7z
Thanks
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I've observed a fairly nasty performance regression when switching to 1.82 related to compression performance that appears to boil down to some very weird/suboptimal machine code being generated.
Del…
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According to Intel SOM, different microarchitectures have different limitations in the use of LEA instructions, aka slow LEA in some cases. But none of current Intel schedule model describes it. It wo…
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I've setup a buildcache to speed up building software, and installing things like Python from it. When going to build py-numpy, it crashes because it uses the compiler paths that python's `sysconfig` …
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Some of our demos (e.g. Meltdown-DE) are microarchitecture-specific, which is something we can't test for at compile time. We could consider using a library like https://github.com/google/cpu_features…
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RVV provides the `__riscv_vset_v_*_*` and `__riscv_vget_v_*_*` intrinsics for not only tuple types but also for vector groups since v0.11, for example:
```C
vint16m4_t __riscv_vset_v_i16m1_i16m4(v…
lsrcz updated
3 weeks ago
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Although CPU microarchitecture details are pulled out of a file, this is currently hard-wired to be `config_ivy_bridge.py`. Since this microarchitecture has no FMA support (and thus no cost associated…
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https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x86-64-Feature-Levels
https://www.phoronix.com/scan.php?page=news_item&px=LLVM-12-Clang-12-Feature-Over
How could this be implemented in …
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The table header of Table 9-3 is in Japanese (though the same table in Japanese PDF is in English).
ahori updated
4 years ago
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Develop an API for Interconnect model and implement an example Interconnect microarchitecture.
Please see https://github.com/riscv-software-src/riscv-perf-model/issues/60#issuecomment-2187718768 fo…
arupc updated
4 months ago