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I have successfully implemented this code on zedboard and monitored the packet over Wireshark. Now I want to process the packet on the PL side. Could you help me with how can I transfer the packet fro…
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Научиться собирать проект, Linux и приложение
EMBV - PYTHON-1300-C Vivado HLS Reference Design
http://zedboard.com/support/design/4681/46
urock updated
8 years ago
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i am implementing Pulissimo project SoC on FPGA. I use Zedboard. I got an error when trying to use openocd to conig jtag for debugging. Please follow the instructions in the readme [https://github.com…
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When I connect to my zedboard I am prompted with "alarm loggin" and then "Password" for both I input "root" but I keep getting the message "Login incorrect".
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Hello,
I synthesized pulpino for the zedboard, and it works fine. I am trying to figure out the clock at which the core is running. I got different information depending on where I look:
- The…
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Thanks for providing your project online, I was trying to reproduce the aes accelerator but apparently part of the project named as "zedboard_project.tgz" is missing. Can you please connect me to the …
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Dear Sir,
I followed your video for interfacing zedboard oled display(part4), I just did it step by step. however it shows an error when generating bitstream. the running sysnthesis and implementat…
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Hi. I created the Image from scratch on the SD Card of my Zedboard. However, Linux is not booting, The image attached shows some information gathered using serial communication.
Do I need to manua…
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in your getting started page you list
"The Ultra96 comes preloaded with Android and can be up and running with a few simple steps:"
however on the [product page](https://www.96boards.org/product/…
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Hi,
I tried to connect to pulpissimo via jtag using openocd, but always get this error:
![398418445_209285052150728_6382659880394201287_n](https://github.com/pulp-platform/pulpissimo/assets/70802909…