-
* [x] kernel functions to read/write samples using RTIO SPI, Zotino
* [x] kernel functions to read/write samples using RTIO SPI, Novogorny
* [x] kernel functions to read/write samples using RTIO SPI…
-
As I mentioned in [issue 10](https://github.com/m-labs/pdq/issues/10), I am running into issues trying to compile the gateware. I was instructed to install ISE Webpack, but I do not believe that to be…
-
Here's a proposed implementation. The proposal at times draws verbatim from Leibrandt & Heidecker (2015) but is distinct to Sayma. See https://arxiv.org/abs/1508.06319
- Each Sayma implements 8 digita…
-
Copied from the pdq directory as requested. I have since also ran it in a python 3.5 environment and got the same error. Could you also please clarify which readme you updated? Looking at the history …
-
OS: 64-bit Windows
Packages migen/misoc and the Xilinx ISE design suite 11.1 installed
----------------------------------------------------------------------
During the compile process by running
…
-
Building .bit from source using
```
commit 440e19b8f9c8ebfce80402a519796cee7fdd6b06
```
I see...
```
$ flterm /dev/ttyUSB2
__ __ _ ____ ____
| \/ (_) ___| ___ / ___|
| |\/…
-
DDS boards arrived.
I plan to do following tests:
- [x] Power supply
- [x] CPLD…
-
Its just a co-incidence but i have been working on FPGA stuff the last week.
Am trying out code generating from golang --> fpga.
I noticed your using m-labs Python parser ( https://github.com/m…
-
This occurs on the Sayma1 board we have on the HK server.
-
What versions of MISOC and MIGEN should I be using for the ARTIQ 2.3 build from source?
Some while back I was using tag/0.3 for both, but that no longer works. With those versions, I get the error…