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Replace the jpeg encoder at https://github.com/timvideos/HDMI2USB-misoc-firmware/tree/master/hdl/encoder/vhdl with cfelton's Verilog version at https://github.com/cfelton/test_jpeg
If https://github.…
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When I run it with one of my toplevel files, git gives this. Where is outvTbgenerator.py
$ python /home/local/NDC/ssheikh/.vscode/extensions/truecrab.verilog-testbench-instance-0.0.5/out\vTbgenerat…
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It would be nice to give our HDL coding examples a uniform style. Ideally, we can find two style guides which are similar between VHDL and Verilog.
For Verilog I'd go with https://github.com/lowRIS…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
4 months ago
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Using GHDL as a frontend for Yosys allows synthesising VHDL, Verilog and/or mixed language designs. See https://im-tomu.github.io/fomu-workshop/mixed-hdl.html. It'd be interesting to test whether this…
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Hello,
How can I add an include path in a way that macros will be found using F12 ? I'm pretty new to vscode so I'm not sure this is a vscode or Verilog-HDL configuration.
For instance, I'm incl…
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Sameer , thanks for the great project.
I am relatively new to Verilog and FPGA development, and I find your work in this field particularly inspiring.
Currently, I am encountering some challenge…
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Hi
I noticed that there are TL to AXI and AXI to TL chisel module in rocket-chip.
Since I neee it for another project, is there any suggestions to convert it to verilog HDL specifically without the …
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It seems that some of the package are not compatible with the runtime environment present in https://colab.research.google.com/.
Installing the following packages with:
```
!curl -O https://repo…
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…