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Dear community,
First of all I want to say thank you for creating this project!
I am a total newcomer to everything related to RISC-V and I find it hard to get started.
So here is what I want…
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Hello,
I followed the wiki (https://github.com/cambridgehackers/zedboard_manifests/wiki/ZedboardAndroid4.1).
When I build, the first error that comes is:
find: 'src': no such file or directory
after…
ghost updated
9 years ago
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Hi,
I have a Zybo z7-10 and a Zedboard and use Vivado 2018.3 and SDK 2018.3 (due to the previous developers of the project).
I'm trying to run the xtrafgen_master_streaming_example.c of the Traf…
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Hi ,
I have designed a zynq + ad9361 board which runs openwifi well .Hareware feature is : ZYNQ XC7Z020CLG400 ,1GB DDR3 memory fo PS, 1G ETHER RJ45 for PS,1G ETHER RJ45 for PL, USB OTG(act as USB ho…
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When I use vivado to synthesis the generated verilog，the command report an error:"module 'system' not found",the error is located at line 139 in rocketchip_wrapper.v.Is there any wrong?Or it lacks som…
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I want to know details about how to implement this .Could you help me？
thank you！
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Hi
I used Numpy code to restore the Image but no matter what Image I used the final result is discoloured and dark. can you help to resolve the issue please?
![woman_srcnn_x3](https://github.com/Fiv…
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Latest build has point to new file but this file is missing from repository
"wilc_type.h:22:31: fatal error: wilc_errorsupport.h: No such file or directory
compilation terminated."
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This list was created by referencing the online RISC-V pipeline tool at https://webriscv.dii.unisi.it/.
Other resources:
http://web.mit.edu/6.111/volume2/www/f2018/run_verilog.html
http://web.mi…
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- [x] Triggering based on custom Verilog in FPGA
- [x] Xilinx interrupt controller configuration on C code side
- [ ] #349
- [ ] #350