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eTeak as the same as its predecessor counterpart, the Balsa synthesis system, reports area estimation of the generated Verilog circuit. However, this highly depends on the utilised cell library (ASI…
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@Dolu1990 , The current MEM blackbox looks like several fixed interface forms(`Ram_1w_1ra` ,`Ram_1w_1rs`,`Ram_1wrs`,`Ram_2wrs`). It may not be suitable for ASIC design
Because of different teams or c…
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**Description**
In sonic 202012, we are observing that COPP TABLE entries are removed from APP_DB by https://github.com/Azure/sonic-utilities/blob/2a982a1fe084b334fb99c372d171273931a0851b/scripts/…
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Hello,
**Type of issue**: bug report
**Impact**: API addition (no impact on existing code)
**Other information**
When SyncReadMem is created with ReadFirst or WriteFirst specified SyncReadMe…
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Found this out while toying with the BM1387;
The asics do not search the entire nonce range. My 2 asic miner splits the 32-bit range to 0x00000000-0x80000000 for the first asic and 0x800000000xffffff…
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Hello,
I have been trying to do an ASIC synthseis of Pulpino but I am facing some difficulties doing so. Mainly I am getting this error in Design Compiler:
Information: /home/aabimbar/pulpino/r…
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#### Description
MC-LAG peer link does not support port interface. Only PortChannel interfaces are supported. But based on Config DB schema in https://github.com/Azure/SONiC/blob/master/doc/m…
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Hello,
I'm trying to reproduce the result of your ASIC design.
The tb.sv of TALCO-XDrop will never stop.
There's no break condition in the second while loop.
Can you please fix it?
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[version]
SONiC Software Version: SONiC.nephos-201911-69879e4-202002261959.0-dirty-20200307.002748
Distribution: Debian 9.12
Kernel: 4.9.0-9-2-amd64
Build commit: 7c915950
Build date: Sat Mar 7 0…
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**Is your request based on a publicly known cryptographic schema and where can we find information about?**
Yes, it's based on BIP-85, which is a way to generate new seeds from an existing seed using…