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I am using the latest version of this repository for a custom RISCOF port. The test fails because the `Zfh/src/flh-align-01.S` test is executed although the `Zfh` ISA extension is not enabled.
* My…
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**The Problem**
I don't know where to fit this information inside this issue so let me put this bit of information first, before I give this huge description of my projects and related issue. Durin…
ucycg updated
6 months ago
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**Describe the bug**
After #883 i discover that neorv32 determines any printed character as "?".
Looks like #883 uart_rx upd broke something
**To Reproduce**
Check "sreg" bus of "rx_engine_t" re…
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Hi @stnolting
According to what we discussed the other day:
> It occurs to me that maybe the arty option can be added to the CI list of implementations.
That would be awesome! Feel free to pro…
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I'm currently exploring the possibility to create an ASIC from a specific NeoRV32 configuration. As I'm still a student without much experience in digital design I still have a lot of things to figure…
ucycg updated
7 months ago
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the `Zbc` sub-extension (carry-less multiplication) is quite different from the other sub-extensions, which really do "bit manipulation" in the more traditional sense...
not critical, but it might …
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Hi
**My question**
I imported NeoRV32 micro controller into a questa simulation project and used `sim/simple/neorv32_tb.simple.vhd` and `sim/simple/uart_rx.simple.vhd` for simulation. I wondered w…
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the proposed `Zc*` extensions described [here](https://github.com/riscv/riscv-code-size-reduction) have recently been ratified....
the `Zca` extensions is of particular interest in "small cores" wi…
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Hi
This is actually a question. I use simple testbench for simulation. What is the best way to capture the value of a variable of C code without using UART to print it?
**Describe the solution you…
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@mikaelsky has suggested (in some issue I cannot find right now) to add a "`*.f`" file that list all required HDL files in their according compile order. This file could be consumed by synthesis tools…