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I recently updated to the newest version of sby and yosys. Now some of the formal proofs generated by SpinalHDL no longer work ([SpinalHDL issue](https://github.com/SpinalHDL/SpinalHDL/issues/1430)). …
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Hello, I'm using spinalHDL to write a cache.
I found the enum string useful for debugging, but it comes with problems:
1. In some components, like dispatching tag data to multiple MSHRs, such co…
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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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Dear Dolu1990
The Nax project is really great!
Its software architecture is very helpful for learning and research, and it also has great application prospects in engineering implementation. I since…
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When including the usb_ohci feature in a build (i.e. for mnt_rkx7 target), litex will clone https://github.com/litex-hub/pythondata-misc-usb_ohci which includes a pre-generated verilog file `UsbOhciWi…
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From the binutils `include/opcode/riscv-opc.h`
```
#define MATCH_MIN 0xa004033
#define MATCH_MAX 0xa005033
#define MATCH_MINU 0xa006033
#define MATCH_MAXU 0xa007033
```
From the riscv-bitmanip …
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I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs.
val decodePc_Domain = ClockDomain(ClockDomain.current.r…
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I was trying this: https://github.com/SpinalHDL/VexRiscv#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator
But got the following error, I tried Some way to solve it but it didn't w…
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prabath@prabath-VirtualBox:~/openocd_riscv$ src/openocd -c 'set VEXRISCV_YAML /home/verilator/Vexriscv/cpu0.yaml' -f tcl/target/vexriscv_sim.cfg
Open On-Chip Debugger 0.10.0+dev-01236-gc974c1b7-dirty…
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I have been looking at our CDC stuff and would like to make a few additions/changes:
# BufferCC
BufferCC is not a safe primitive to use in general. It's totally fine as a basic building block an…