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We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…
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The following procedure: https://github.com/hdl/containers/blob/442f15fd80ee5d2935602880c59b6b8ff2077f22/debian-bullseye/vtr.dockerfile#L47-L52
```bash
git clone https://github.com/verilog-to-rout…
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**Description**
I am hitting this assertion and erroring out
https://github.com/YosysHQ/yosys/blob/41b34a19353dbbe00aa08f3561e25e0bfa4c84d2/kernel/mem.cc#L473C5-L473C33
```
if ((port.transparency_…
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@drichmond @mjacobsen
https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/chnl_tester.v#L128 is only cheating the receiving part. This means **we are not actually using the actual data r…
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Hi Nic
I found `hdlConvertor` interesting for my coming project (on Python generated SV), and would like to use it.
However, I would like my user can use `hdlConvertor` directly from a simple `pip…
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I'm getting a syntax error when using a function call that creates a signal inside an Elif.
I can understand why this kind of function call might be problematic in a Python DSL, however I'm raising…
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Xilinx newbie, but I ran source build_all.tcl and ended up with
```
Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include
^
1 error…
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Hi I'm a freshman of HDL, our Compilers Principles teacher ask us to study how to translate nMigen into RTLIL, then translate it into
Verilog. Could you give me a guide on how to read your back trans…
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Synopsys VCS-MX supports not only (System)Verilog as is the case with the backend right now but also VHDL, allowing mixed-language simulation.
Some pointers:
- http://www.vlsiip.com/vcs/
- http://s…
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We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.
## 1. Suppo…