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**Issue by [JarrettBillingsley](https://github.com/JarrettBillingsley)**
_Tuesday Dec 31, 2019 at 19:17 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/289_
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This is a questi…
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This is a question!
I've been learning FPGA design on an iCEStick with nMigen. I haven't had more than "toy-level" experience with Verilog or with the yosys-nextpnr toolchain. The problem I keep ru…
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Hi,
Experimenting with the framework, a simple blink using the SB_HFOSC module would not verify using `apio verify`.
blink.v
```verilog
module blinky (output wire BLUn,
output …
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Meeting time: 4:00PM UTC
Please comment for next meeting's agenda items:
@glikely
@mwelling
@ric96
@sdrobertw
@krisik70
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ric96 updated
5 years ago
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I'm stoked you're using the open source Verilog toolchain and wanted to see how much effort it would take to create a BlackIce board compatibility profile?
https://www.tindie.com/products/Folknolog…
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## Steps to reproduce the issue
Given a file called [simple_computer.txt](https://github.com/YosysHQ/yosys/files/3836471/simple_computer.txt) (originally called simple_computer.v but GitHub doesn't…
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Synthesizing the following example with `ghdl --synth function_test` seems to produce valid output. However, `yosys -m ghdl -p 'ghdl function_test; synth_ice40'` fails with:
```
-- Running command…
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fedora 30 /usr/local/src for default directory
yosys, arachne-pnr, icestorm from repositories
yosys -V
Yosys 0.8 (git sha1 UNKNOWN, gcc 9.0.1 -O2 -fexceptions -fstack-protector-s…
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Tristan, thanks again for GHDL and working to make opensource synthesis possible!
I've been testing multiple pieces of code, trying to get a feel for what is still to be done before we can synthesi…