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PR #41 highlighted the need for AXI snippets. @Bochlin provided a starting point for the requirements of such snippets. Their comment is reported below, and this issue is the place to discuss this top…
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In [hwh_frontend.py](../blob/main/pynqmetadata/frontends/hwh_frontend.py)(line 485ff) there is a check, tries to map the "INTERFACE" to a portname.
If there is a AXI_Full port, the `INTERFACE` prope…
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**Description**
I've compiled OSVVM libraries using ghdl/synth:formal docker image. Testbenches defined in osvvm/Demo folder works fine with GHDL. Then, I tried AXI4 example of OSVVM. Files pass anal…
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When generating a ram controller with an Axi interface, the awsize and arsize ports are 4 bits wide
```verilog
input wire [3:0] user_port_axi_0_awsize,
```
```verilog
input wire …
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Some of our CHERI Flute/Toooba CI jobs recently started failing. After some investigation, I decided that it was probably appropriate to open an issue here regarding what I observe. The TLDR:
```
…
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I'm looking at adding some support for ACE 4 on top of the `amba4.axi` classes we already have in `spinal.lib`, but I'm not super sure on what's the best way to proceed here. ACE adds two extra chann…
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Hi @alexforencich ,
I am trying to integarte one of your ethernet module (specifically eth_mac-10g_fifo) with my system on chip. In my SoC I have used the AXI4 as the system bus. I have my own wrappe…
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svUnit is a library so I thing without github clone method we can do it in over server or edaplayground, only we need to import svUnit pkg and include macro file.
Here show as how to enable the wav…
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Hi. I was hoping I could get some examples of fsva use, particularly using xsim/Vivado using some of the features listed on the ReadMe, such as OSVVM.
Also I was wondering if this tool could ouput …
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Let us collect the changes required to harmonize ports and parameters and to minimize incompatibilities with EDA tools. Those changes will be breaking (as in "backwards-incompatible"), so let us make…