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Hello,
I found that read access to the Rx memory allocated by the driver is slow too.I have already referred to the issue:[https://github.com/bperez77/xilinx_axidma/issues/69](url)
In my app,i dis l…
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When running axidma_transfer (or the benchmark example) on PetaLinux 2017.2, I am getting "axidma: axidma_dma.c: axidma_start_transfer: 305: DMA receive transaction timed out".
My Vivado 2017.2 desi…
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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Hi,
I'm trying to transfer data from PL to PS using the AXI DMA IP (with SG) using this xilinx_axidma driver.
The first test I did is the loopback test. For this test, I've connected the M_AXIS_…
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Hi Brandon-san,
I'm trying to use your driver on my board, xilinx system(xilinx-v2014.4).
When i run insmod axidma.ko command to load driver,the error in the title comes up.
The error log as fo…
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Hi I compiled your module with petalinux 2020. I'm configured device tree with this code:
`
/{
axidma_chrdev: axidma_chrdev@0 {
compatible = "xlnx,axidma-chrdev";
dmas = ;
dma-name…
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I'm running your driver on an xilinx embedded linux (built w/ petalinux 2017.3) and a Zynq Ultrascale device, and when I run the speed test /loopback test, dma_map_sg returns 0 and errors out. My HW i…
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I did just a short test, but get a read timeout, see below. Do I need to change the example code somehow?
```
root@te0715_linux:~# modprobe xilinx_axidma
xilinx_axidma: loading out-of-tree module t…
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Hello!
I'm working on a design where I will be receiving data in the PL and I'm using a DMA to pass it to the PS. The DMA only has the write channel activated. This is my Vivado design:
![image]…
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0. Could you send email to [xianjun.jiao@ugent.be](mailto:xianjun.jiao@ugent.be) to introduce your self?
Sent
1. Our image is used directly or you build your own image?
I used the image "openwifi…