AW5178 / riscv-implementations

A repository where I explore various implementations of the RISC-V ISA in SystemVerilog.
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Define Instruction Set and Document Implementation #1

Open AW5178 opened 8 months ago

AW5178 commented 8 months ago

The first portion of this project entails the analysis of the RISC-V instruction set and picking the instructions that I want to implement. As a rule of thumb, I'm going to stick to 32-bit operations for both integer and floating-point instructions. This means that all FP ops that I want to implement will be single precision.

I will document Bit Fields and instruction execution.