Closed rod-chapman closed 4 years ago
Closes #365
This PR covers addition of support for the implementation-defined performance counters supported by the E31 RISCV core in the HiFive FE310_* series of SoCs, present in the HiFive1 and HiFive1_RevB boards.
Opened in error - should have been a Pull Request not a new Issue...
Closes #365
This PR covers addition of support for the implementation-defined performance counters supported by the E31 RISCV core in the HiFive FE310_* series of SoCs, present in the HiFive1 and HiFive1_RevB boards.