Arty A7 High Speed PMOD ports can cause cross-talk in current gateware layout

[AdamMooers]

The PMOD outputs will need to be re-arranged to avoid using the high speed differential outputs as single-ended outputs since this can cause significant crosstalk:

https://github.com/AdamMooers/upsilon/blob/cf95a0fd200cf3ba6926b776239be793abf57f18/gateware/soc.py#L67

https://digilent.com/reference/programmable-logic/arty-a7/reference-manual

A few possibilities:

• The select lines are not necessary because each ADC/DAC is on a separate SPI bus
• The ADCs(or possibly the DACs?) don't require MISO lines

It would probably be best to avoid the high-speed differential outputs altogether unless the application shows it to be necessary.

[mcgoron-peter]

soc.py has a setting to drive one part of the differential output low (I also noticed it's spelled incorrectly...), which is what the manual recommends. I think I messed up which pins are a part of which pair so the file has to be changed to the correct outputs, but there will still be enough pins for 8 DACs and 8 ADCs.

[AdamMooers]

A few of the pins on PMOD B and C needed to be rearranged to prevent cross-talk. The comment about grounding was helpful. Thanks!

See ada800a6654378492d7a015fd21d6139a67b9e99

(I am planning to start committing future changes using gitflow but this commit is directly into the picorv32 branch)