Artoriuz / maestro

A 5 stage-pipeline RV32I implementation in VHDL
MIT License
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MODELSIM COMPILATION ERROR #2

Closed HollaHieu closed 3 years ago

HollaHieu commented 3 years ago

Hello ,

I am trying to compile and run the project on ModelSim for simulation. I am a bit clueless on how to run your project because I am also a newbie in VHDL :).

What I have done so far to run the project is add all the source vhd files in "./Project/Components" to a new project in ModelSim and try to compile all. However, after compilation, this message appears "28 compiles, 14 failed with 124 errors.". I can send the error log in ModelSim for you. But I think I must be doing something wrong. Also, I can't seem to find the testbench file for ModelSim simulation.

Can you help me to run this project? Thank you, Hieu

Artoriuz commented 3 years ago

Hi, when I simulated it I did it entirely within Quartus using the ModelSim version that's embedded into it. You should be able to easily create a waveform file and add the signals that you want into it.

On Tue, 24 Aug 2021, 13:57 HollaHieu, @.***> wrote:

Hello ,

I am trying to compile and run the project on ModelSim for simulation. I am a bit clueless on how to run your project because I am also a newbie in VHDL :).

What I have done so far to run the project is add all the source vhd files in "./Project/Components" to a new project in ModelSim and try to compile all. However, after compilation, this message appears "28 compiles, 14 failed with 124 errors.". I can send the error log in ModelSim for you. But I think I must be doing something wrong. Also, I can't seem to find the testbench file for ModelSim simulation.

Can you help me to run this project? Thank you, Hieu

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HollaHieu commented 3 years ago

Great thanks for your reply Artoriuz!

I managed to open the .qpf project file in Quartus prime lite version 20.1. However, during compilation & synthesis, I encounter the following bug:

"Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis".

I wonder if this is because of version mismatch between Quartus lite 20.1 and 18.1? Or do I have to do some extra config/changes before running the project?

Thanks, Hieu

HollaHieu commented 3 years ago

Hi sorry for the quick follow up message,

I have downloaded Quartus prime lite version 18.01 and the Cyclone IV device support (including Cyclone IV GX FPGA) and managed to compile and overcome the previous mentioned bug. But now I ran into this problem when compiling design: The problem is in the Filter (Place & Route) stage

"Error (119027): Design requires 521 I/O Output Buffer resources -- too many to fit in 479 available in the selected device or any device in the device family"

"Error (119003): Cannot find device that meets Compiler settings specifications"

Do you have any thoughts on this? Thank you, Hieu

HollaHieu commented 3 years ago

Hi, I have overcome the above issue by 1) Installing Quartus & ModelSim Lite 18.01 2) Assigning all the physical pins (except clk pins) as virtual pins like in this video: https://www.youtube.com/watch?v=QET0lC-jdAQ (or search "Virtual Pin Assignments in a Partial Design" in Youtube)

Now, I have compiled & synthesized the project successfully! However, I still don't know how to run the simulation in ModelSim through Quartus. I have added the path of ModelSim to Quartus and open the simulation window. However, there is no work library for me to add any waves or create any waveform file as shown.

ảnh

I would greatly appreciate any help on ModelSim simulation from Quartus for the project. Thanks

Artoriuz commented 3 years ago

Try following this video: https://youtu.be/a8JAkKhxlQI I know it's quite old, but I think it's still pretty representative of how the GUI looks like in the current Quartus version.

On Wed, Aug 25, 2021 at 9:36 AM HollaHieu @.***> wrote:

Hi, I have overcome the above issue by

  1. Installing Quartus & ModelSim Lite 18.01
  2. Assigning all the physical pins (except clk pins) as virtual pins like in this video: https://www.youtube.com/watch?v=QET0lC-jdAQ (or search "Virtual Pin Assignments in a Partial Design" in Youtube)

Now, I have compiled & synthesized the project successfully! However, I still don't know how to run the simulation in ModelSim through Quartus. I have added the path of ModelSim to Quartus and open the simulation window. However, there is no work library for me to add any waves or create any waveform file as shown.

[image: ảnh] https://user-images.githubusercontent.com/43841523/130791315-bd089a9b-0854-434e-bc18-efd4c651c1e4.png

I would greatly appreciate any help on ModelSim simulation from Quartus for the project. Thanks

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/Artoriuz/maestro/issues/2#issuecomment-905462857, or unsubscribe https://github.com/notifications/unsubscribe-auth/AC4EY4N5JA573N4DTNSQNLLT6TPTPANCNFSM5CXIDFVA . Triage notifications on the go with GitHub Mobile for iOS https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675 or Android https://play.google.com/store/apps/details?id=com.github.android&utm_campaign=notification-email .

HollaHieu commented 3 years ago

Thank you so much for your video referencing! Now I run into the trouble of finding the Vector Source File :( here is the bug:

"Error (199014): Vector source file D:/Sach/20202/ComputerArchitecture/maestro-master/Quartus/riscv_microcontroller/Waveform.vwf specified with --testbench_vector_input_file option does not exist"

ảnh

Is there anyway you and I can connect to Discord or something for really quick exchange. I know it's a lot to ask but I really want to run this project :( .

Thank you, Hieu

Artoriuz commented 3 years ago

I've done a quick google search here and multiple possible solutions for this have been suggested elsewhere. I'll be closing this since it has nothing to do with the project, just with Quartus itself.