gjkunde
commented
3 years ago CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_intc_0/intr
narrucmot
I am getting the following warnings after cloning branch 2020.1 of hdf and petalinux and master for bdf
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_bram_ctrl_0/S_AXI(0) and /ps8_0_axi_periph/xbar/M00_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m01_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m02_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M02_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m03_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M03_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m04_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M04_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m05_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M05_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m06_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M06_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m07_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M07_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m08_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M08_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/m09_couplers/auto_ds/S_AXI(0) and /ps8_0_axi_periph/xbar/M09_AXI(16) CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_intc_0/intr
</home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addra'(32) to pin: '/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addrb'(32) to pin: '/axi_bram_ctrl_0/bram_addr_b'(13) - Only lower order bits will be connected. VHDL Output written to : /home/gjkunde/Avnet/hdl/Projects/ultra96v2_oob/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/synth/ULTRA96V2.vhd WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addra'(32) to pin: '/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addrb'(32) to pin: '/axi_bram_ctrl_0/bram_addr_b'(13) - Only lower order bits will be connected.