typo in the verilog file : MappedSPIFlash.v

BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

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typo in the verilog file : MappedSPIFlash.v #41

Closed KiranKanchi closed 3 years ago

KiranKanchi commented 3 years ago

Dear Bruno,

Seems there is an unexpected semicolon when running "make ICESTICK" from FemtoRV example as seen below :

RTL/DEVICES/MappedSPIFlash.v:306: ERROR: syntax error, unexpected ';'

/*****/

function [15:0] bbyyttee; input [7:0] x; begin bbyyttee = { x[7],x[7],x[6],x[6],x[5],x[5],x[4],x[4], x[3],x[3],x[2],x[2],x[1],x[1],x[0],x[0] };
end endfunction; <-- here

/****/ Kind regards KiranKanchi

BrunoLevy commented 3 years ago

You are perfectly right ! (yosys does not complain, but iverilog indicates a syntax error). Fixed.