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CHERIoT-Platform / cheriot-sail

Sail code model of the CHERIoT ISA
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Incorrect behaviour when registers greater than 15 used as destination in certain instructions #67

Open rmn30 opened 1 month ago

rmn30 commented 1 month ago

@mndstrmr points out in https://github.com/microsoft/cheriot-ibex/issues/30 that the sail behaves incorrectly in cases where registers greater than 15 (which are not valid in RV32E) are used in instructions that have side-effects other than writing the destination register such as CSRRW. This is due to the way that we use a Sail exception in the register read / write functions to detect the invalid register rather than detecting it during decode. This was for expedience i.e. to avoid many changes to the upstream sail-riscv repo.

It would be best if the upstream had support for RV32E. In fact we could do with clarification of the RISC-V specification as there are two reasonable interpretations at the moment:

  1. raise a reserved instruction exception (i.e. fail at decode stage)
  2. ignore the top bit of the register fields

We are attempting to implement 1. and Ibex used to do 2. 2 is easier to implement but probably less useful.

rmn30 commented 1 month ago

https://github.com/riscv/sail-riscv/issues/523 filed upstream. I looked again at the latest RISC-V spec and it does say that the unused encodings are reserved i.e. should cause a reserved instruction exception.