How much do the PR code changes differ from the unmodified code?
[X] bit for bit for intel, gnu, intelclassic
[X] different at roundoff level for cray, nvhpc
[ ] more substantial
Does this PR create or have dependencies on Icepack or any other models?
[ ] Yes
[X] No
Does this PR update the Icepack submodule? If so, the Icepack submodule must point to a hash on Icepack's main branch.
[ ] Yes
[X] No
Does this PR add any new test cases?
[ ] Yes
[X] No
Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/. A test build of the technical docs will be performed as part of the PR testing.)
[X] Yes
[ ] No, does the documentation need to be updated at a later time?
[ ] Yes
[ ] No
[X] Please document the changes in detail, including why the changes are made. This will become part of the PR commit log.
Update derecho port
update inteloneapi, validate, use -O1, problems with -check all.
update cray to ncarenv/23.09 and cce/16.0.1, answers change
update intel to ncarenv/23.09 and intel/2023.2.1, answer bit-for-bit
update nvhpc to ncarenv/23.09 and nvhpc/23.7, answers change
update queue so smaller jobs go into develop (shared) instead of main
Add ifndef __INTEL_LLVM_COMPILER (for intel oneapi) around an OMP loop that the compiler doesn't handle properly (reported to intel) in ice_history.F90.
Update QC documentation in the user guide to clarify where/how to run the cice.t-test.py script.
PR checklist
Update derecho port
Add ifndef __INTEL_LLVM_COMPILER (for intel oneapi) around an OMP loop that the compiler doesn't handle properly (reported to intel) in ice_history.F90.
Update QC documentation in the user guide to clarify where/how to run the cice.t-test.py script.