I am trying to design a simple sequential logic circuit, and tried with a flip-flop. It gave an Java segfault when I try to connect the two NOR gates to each other. I have created a github repo here to demo the problem : https://github.com/sness23/cello-sequential
The Java stacktrace is:
Generating Graphviz representation of design.
Writing dot description to `/root/output/subleq_yosys.dot'.
Dumping module and_gate to page 1.
Exec: dot -Tpdf '/root/output/subleq_yosys.dot' > '/root/output/subleq_yosys.pdf.new' && mv '/root/output/subleq_yosys.pdf.new' '/root/output/subleq_yosys.pdf'
Executing EDIF backend.
Executing JSON backend.
End of script. Logfile hash: bfb12311a5
CPU: user 0.01s system 0.00s, MEM: 19.67 MB total, 10.30 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 47% 3x read_verilog (0 sec), 11% 4x opt_expr (0 sec), ...
15:56:11.297 [main] INFO Yosys -
Exception in thread "main" java.lang.NullPointerException
at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubCircuitInputs(subCircuitEnumerator.java:81)
at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubCircuitInputs(subCircuitEnumerator.java:87)
at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubNetlistDetailsGraph(subCircuitEnumerator.java:258)
at org.cellocad.BU.subcircuit.subCircuitSwap.nodeRewrite(subCircuitSwap.java:105)
at org.cellocad.BU.subcircuit.subCircuitSwap.implementSwap(subCircuitSwap.java:71)
at org.cellocad.BU.netsynth.NetSynth.runSubCircSwap(NetSynth.java:759)
at org.cellocad.BU.netsynth.NetSynth.getNetlistCode(NetSynth.java:617)
at org.cellocad.BU.netsynth.NetSynth.getNetlist(NetSynth.java:564)
at org.cellocad.BU.netsynth.NetSynth.runNetSynth(NetSynth.java:515)
at org.cellocad.BU.netsynth.NetSynth.runNetSynth(NetSynth.java:501)
at org.cellocad.v2.logicSynthesis.algorithm.Yosys.NetSynthUtils.getNetSynthNetlist(NetSynthUtils.java:295)
at org.cellocad.v2.logicSynthesis.algorithm.Yosys.Yosys.postprocessing(Yosys.java:282)
at org.cellocad.v2.common.algorithm.Algorithm.execute(Algorithm.java:90)
at org.cellocad.v2.common.runtime.RuntimeObject.executeAlgo(RuntimeObject.java:375)
at org.cellocad.v2.logicSynthesis.runtime.LSRuntimeObject.runAlgo(LSRuntimeObject.java:182)
at org.cellocad.v2.common.runtime.RuntimeObject.execute(RuntimeObject.java:403)
at org.cellocad.v2.DNACompiler.runtime.Main.main(Main.java:169)
I am trying to design a simple sequential logic circuit, and tried with a flip-flop. It gave an Java segfault when I try to connect the two NOR gates to each other. I have created a github repo here to demo the problem : https://github.com/sness23/cello-sequential
The Java stacktrace is:
Generating Graphviz representation of design. Writing dot description to `/root/output/subleq_yosys.dot'. Dumping module and_gate to page 1. Exec: dot -Tpdf '/root/output/subleq_yosys.dot' > '/root/output/subleq_yosys.pdf.new' && mv '/root/output/subleq_yosys.pdf.new' '/root/output/subleq_yosys.pdf'
Executing EDIF backend.
Executing JSON backend.
End of script. Logfile hash: bfb12311a5 CPU: user 0.01s system 0.00s, MEM: 19.67 MB total, 10.30 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 47% 3x read_verilog (0 sec), 11% 4x opt_expr (0 sec), ...
15:56:11.297 [main] INFO Yosys - Exception in thread "main" java.lang.NullPointerException at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubCircuitInputs(subCircuitEnumerator.java:81) at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubCircuitInputs(subCircuitEnumerator.java:87) at org.cellocad.BU.subcircuit.subCircuitEnumerator.getSubNetlistDetailsGraph(subCircuitEnumerator.java:258) at org.cellocad.BU.subcircuit.subCircuitSwap.nodeRewrite(subCircuitSwap.java:105) at org.cellocad.BU.subcircuit.subCircuitSwap.implementSwap(subCircuitSwap.java:71) at org.cellocad.BU.netsynth.NetSynth.runSubCircSwap(NetSynth.java:759) at org.cellocad.BU.netsynth.NetSynth.getNetlistCode(NetSynth.java:617) at org.cellocad.BU.netsynth.NetSynth.getNetlist(NetSynth.java:564) at org.cellocad.BU.netsynth.NetSynth.runNetSynth(NetSynth.java:515) at org.cellocad.BU.netsynth.NetSynth.runNetSynth(NetSynth.java:501) at org.cellocad.v2.logicSynthesis.algorithm.Yosys.NetSynthUtils.getNetSynthNetlist(NetSynthUtils.java:295) at org.cellocad.v2.logicSynthesis.algorithm.Yosys.Yosys.postprocessing(Yosys.java:282) at org.cellocad.v2.common.algorithm.Algorithm.execute(Algorithm.java:90) at org.cellocad.v2.common.runtime.RuntimeObject.executeAlgo(RuntimeObject.java:375) at org.cellocad.v2.logicSynthesis.runtime.LSRuntimeObject.runAlgo(LSRuntimeObject.java:182) at org.cellocad.v2.common.runtime.RuntimeObject.execute(RuntimeObject.java:403) at org.cellocad.v2.DNACompiler.runtime.Main.main(Main.java:169)