VHDL syntax highlighting

[GoogleCodeExporter]

At the moment (gerrit 2.11.1), VHDL syntax highlighting is not supported by the 
change screen. Is there any chance that this will by integrated into gerrit at 
some point?

If not, is there a way how we could extend gerrit to support VHDL syntax 
highlighting, e.g. by a plugin?

Original issue reported on code.google.com by roman.ka...@gmail.com on 23 Jun 2015 at 12:05

[GoogleCodeExporter]

Gerrit is using CodeMirror for SideBySide view. It seems that VHDL language is 
not supported
by CodeMirror atm: [1]. However, in this post to their dev ML adjustment to 
Verilog mode was
published, that should work for VHDL as well: [2]. So you could try to build 
custom Codemirror
version and include this patch and verify if it works.

AFAICT, the maintainers of CodeMirror project also accept sponsoring for 
implementing new
language modes. You may want to contact them and ask. Once CodeMirror supports 
VHDL
it would be very easy to extend Gerrit to support it as well.

You cannot add new language mode in Gerrit plugin, atm.

* [1] https://codemirror.net/mode/index.html
* [2] https://groups.google.com/d/topic/codemirror/uRUuqXimqj0/discussion

Original comment by David.Os...@gmail.com on 23 Jun 2015 at 12:18

• Changed state: AwaitingInformation

[GoogleCodeExporter]

As workaround for now you could use Unified diff view instead of SideBySide 
diff view.

Original comment by David.Os...@gmail.com on 24 Jun 2015 at 7:33