Performance trackers - Githubissues

ChrisShakkour / RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

MIT License

8 stars 1 forks source link

Performance trackers #35

Open ChrisShakkour opened 3 years ago

ChrisShakkour commented 3 years ago

IPC retired instructions per net Cycles. to plot graph performance

amichai-bd commented 2 years ago

I recommend having a SystemVerilog counter - for now in the TB env (once you implement CSR - you will base it in the FE HW) You can use XMR (cross module reference) access from the TB to the core HW indications to calculate the differet PMONs (performance monitors). Example:

Data Hazard (with Not Insertion)
Jumps
Branches (taken or not)
in general number of cycle until ebreake At EOT (end of test) You can "dump" the "SystemVerilog counter" to one of your logs to get stats on your run. @shahardror1 @ChrisShakkour