ChrisShakkour / RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
MIT License
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Boot flow validation #72

Closed ChrisShakkour closed 2 years ago

ChrisShakkour commented 2 years ago

Force reset when core is executing a program

When reset is asserted core shall reset control registers, pc and cpu go register, and halt on pc adress 0x00 until tb triggers core execution.

When trigger is asserted boot flow shall execute and run program.