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ChrisShakkour / RV32I-MAF-project

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
MIT License
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RTL simulation automatic flow #75

Open ChrisShakkour opened 2 years ago

ChrisShakkour commented 2 years ago

to create a snapshot, when simulating RTL tb, to do the following stages automatically in the OUTPUT directory

  1. compile and Build c-test. (compile_gcc)
  2. simulate c test. (simulate_c_test)
  3. compile TB RTL. (compile_hdl)
  4. simulate RTL. (simulate)
  5. compare c test simulation with RTL simulation results, and report pass/fail results.