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CommonEvaluationPlatform / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
BSD 3-Clause "New" or "Revised" License
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Attempting to run the Baremetal tests with CEP (v4.7) using Xcelium (23.09.006) fails #38

Open jordankrim opened 3 months ago

jordankrim commented 3 months ago

I go into for example sims/cep_cosim/testSuites/baremetaltests/aesMacro and do a: make all

The simulator seems to load OK but then it errors out. It looks initially like something is wrong in c_dispatch that didn't happen in v4.4. Then there is a fatal error with GLIB and another error with get_v2c_mail. Not sure why all these are occurring because v4.4 works fine:

CEP_COSIM: ---------------------------------------------------------------------- CEP_COSIM: Common Evaluation Platform Co-Simulation Environment
CEP_COSIM: ---------------------------------------------------------------------- CEP_COSIM: CEP_COSIM: Operating System: Red Hat Enterprise Linux 8.10 (Ootpa) CEP_COSIM: Running non-ASIC test with the following variables: CEP_COSIM: RISCV = /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools) CEP_COSIM: VMGR_PATH = /mnt/data/cadtools/cds/vmanager/23.09.002 CEP_COSIM: XCELIUM_INSTALL = /mnt/data/cadtools/cds/xcelium/23.09.006 CEP_COSIM: CHIPYARD_SUB_PROJECT = cep_cosim CEP_COSIM: CHIPYARD_CPU_COUNT = 4 CEP_COSIM: MODELSIM = 0 CEP_COSIM: CADENCE = 1 CEP_COSIM: DUT_SIM_MODE = BARE_MODE CEP_COSIM: RISCV_TESTS = 0 CEP_COSIM: NOWAVE = 1 CEP_COSIM: PROFILE = 0 CEP_COSIM: COVERAGE = 0 CEP_COSIM: USE_GDB = 0 CEP_COSIM: TL_CAPTURE = 0 CEP_COSIM: VIRTUAL_MODE = 0 CEP_COSIM: BYPASS_PLL = 0 CEP_COSIM: DISABLE_CHISEL_PRINTF = 1 CEP_COSIM: BAREMETAL_PRINTF = none CEP_COSIM: OPENOCD_ENABLE = 0 CEP_COSIM: NOLLKI_MODE = 0

/opt/rh/gcc-toolset-13/root/usr/bin/g++ -DRISCV_WRAPPER=\"./riscv_wrapper.img\" -DNOWAVE -DCHIPYARD_CPU_COUNT=4 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/src -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/cep_tests -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/diag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/share -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/simDiag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli -I /mnt/data/cadtools/cds/xcelium/23.09.006/tools/include -DTL_CAPTURE=0 -DVECTOR_D=\"/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/vectors\" -g -std=gnu++11 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/include -L /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/lib -Wno-format -Wno-narrowing -DBIG_ENDIAN -DSIM_ENV_ONLY -D_SIM_SW_ENV -I. -c -o c_dispatch.o c_dispatch.cc c_dispatch.cc: In function ‘int main(int, char**)’:

: **warning: ISO C++ forbids converting a string constant to ‘char*’ [-Wwrite-strings] c_dispatch.cc:64:24: note: in expansion of macro ‘RISCV_WRAPPER’ 64 | errCnt += loadMemory(RISCV_WRAPPER, fileOffset, destOffset, maxByteCnt);** | ^~~~~~~~~~~~~ /opt/rh/gcc-toolset-13/root/usr/bin/g++ -DRISCV_WRAPPER=\"./riscv_wrapper.img\" -DNOWAVE -DCHIPYARD_CPU_COUNT=4 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/src -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/cep_tests -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/diag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/share -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/simDiag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli -I /mnt/data/cadtools/cds/xcelium/23.09.006/tools/include -DTL_CAPTURE=0 -DVECTOR_D=\"/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/vectors\" -g -std=gnu++11 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/include -L /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/lib -Wno-format -Wno-narrowing -DBIG_ENDIAN -DSIM_ENV_ONLY -D_SIM_SW_ENV -I. -c -o c_module.o c_module.cc /opt/rh/gcc-toolset-13/root/usr/bin/g++ -DRISCV_WRAPPER=\"./riscv_wrapper.img\" -DNOWAVE -DCHIPYARD_CPU_COUNT=4 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/src -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/cep_tests -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/diag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/share -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/simDiag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli -I /mnt/data/cadtools/cds/xcelium/23.09.006/tools/include -DTL_CAPTURE=0 -DVECTOR_D=\"/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/vectors\" -g -std=gnu++11 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/include -L /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/lib -Wno-format -Wno-narrowing -DBIG_ENDIAN -DSIM_ENV_ONLY -D_SIM_SW_ENV -I. -c -o riscv_wrapper.o riscv_wrapper.cc /opt/rh/gcc-toolset-13/root/usr/bin/g++ -DRISCV_WRAPPER=\"./riscv_wrapper.img\" -DNOWAVE -DCHIPYARD_CPU_COUNT=4 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/src -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/cep_tests -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/diag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/share -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/simDiag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli -I /mnt/data/cadtools/cds/xcelium/23.09.006/tools/include -DTL_CAPTURE=0 -DVECTOR_D=\"/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/vectors\" -g -std=gnu++11 -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/include -L /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/../../.conda-env/lib -Wno-format -Wno-narrowing -DBIG_ENDIAN -DSIM_ENV_ONLY -D_SIM_SW_ENV -B/usr/bin -o c_dispatch ./c_dispatch.o ./c_module.o ./riscv_wrapper.o /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/v2c_lib.a -lpthread -lcryptopp /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/riscv64-unknown-elf-gcc -DNOWAVE -DCHIPYARD_CPU_COUNT=4 -mcmodel=medany -O2 -fno-common -fno-builtin-printf -fno-builtin-puts -Wall -Wno-unused-function -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/bare -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/bare/include -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/vectors -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/src -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/cep_tests -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/diag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/share -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/simDiag -I /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli -I /mnt/data/cadtools/cds/xcelium/23.09.006/tools/include -DBARE_MODE -DRISCV_CPU -mabi=lp64 -march=rv64ima_zicsr_zifencei -static -nostdlib -nostartfiles -T /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/drivers/bare/cep_link.lds riscv_wrapper.cc /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libriscv.a -o riscv_wrapper.elf riscv_wrapper.cc: In function 'void thread_entry(int, int)': riscv_wrapper.cc:59:9: warning: unused variable 'revCheck' [-Wunused-variable] 59 | int revCheck = 1; | ^~~~~~~~ /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/../lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: riscv_wrapper.elf has a LOAD segment with RWX permissions /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/riscv64-unknown-elf-objdump -S -C -d -l -x riscv_wrapper.elf > riscv_wrapper.dump /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/riscv64-unknown-elf-objcopy -O binary --change-addresses=-0x80000000 riscv_wrapper.elf riscv_wrapper.img /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/scripts/smartelf2hex.sh riscv_wrapper.elf > riscv_wrapper.hex /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/bin/vpp.pl /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/c_dispatch 1 1 testHistory.txt 0 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/macroMix_sim_xrun.log 0 \""/mnt/data/cadtools/cds/xcelium/23.09.006/tools/bin/64bit/xrun -64bit -R -xmlibdirname /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d -afile /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli/v2c.tab -loadpli1 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -sv_lib /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -loadvpi /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d/run.d/librun.so:boot -log /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/macroMix_sim_xrun.log"\" use_gdb flags = 0 old_seed=46755414 status=FAIL updateInfo=1 notFound=0 Using old seed=0x46755414 From Parent PID=2754163 From Child PID=2754167 EXEC: /mnt/data/cadtools/cds/xcelium/23.09.006/tools/bin/64bit/xrun -64bit -R -xmlibdirname /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d -afile /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli/v2c.tab -loadpli1 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -sv_lib /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -loadvpi /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d/run.d/librun.so:boot -log /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/macroMix_sim_xrun.log Executing /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/c_dispatch 0x46755414 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/c_dispatch: /mnt/data/cadtools/cds/spb/23.10.002/tools.lnx86/lib/64bit/libstdc++.so.6: version `GLIBCXX_3.4.32' not found (required by /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/c_dispatch) run_caller_cmds::Status return is 256 run_caller_cmds::Total errCnt is 1 TOOL: xrun(64) 23.09-s006: Started on Aug 16, 2024 at 17:06:50 EDT xrun(64): 23.09-s006: (c) Copyright 1995-2024 Cadence Design Systems, Inc. Loading snapshot worklib.cep_tb:sv .................... Done **xmsim: *W,NOLDPI: Unable to load /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so. OSDLERROR: /mnt/data/cadtools/cds/xcelium/23.09.006/tools.lnx86/inca/bin/64bit/../../../lib/64bit/libstdc++.so.6: version `GLIBCXX_3.4.32' not found (required by /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so). get_v2c_mail(__mSlotId, __mCpuId, inBox); | xmsim: *F,NOFDPI (/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/dvt/dpi_common.incl,331|15): Function get_v2c_mail not found in any of the shared object specified with -SV_LIB switch. The corresponding import DPI declaration is done in file /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/dvt/dpi_common.incl at line no. 28.** TOOL: xrun(64) 23.09-s006: Exiting on Aug 16, 2024 at 17:06:50 EDT (total: 00:00:00) Going to sleep for 20 seconds for the simv to finish cleaning up like coverage dumping kill_all_threads::Terminating Simv process "/mnt/data/cadtools/cds/xcelium/23.09.006/tools/bin/64bit/xrun -64bit -R -xmlibdirname /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d -afile /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli/v2c.tab -loadpli1 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -sv_lib /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -loadvpi /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d/run.d/librun.so:boot -log /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/macroMix/macroMix_sim_xrun.log" with commad=kill 2754167 make: *** [/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/common.make:274: .vrun_flag] Error 255
jordankrim commented 3 months ago

Somehow the GLIBCXX was incorrect. I changed my g++ compiler from /opt/rh/gcc-toolset-13 to /opt/rh/gcc-toolset-13 in the sims/cep_cosim/common.make. This got me a little further but now I get this:

/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/../lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: riscv_wrapper.elf has a LOAD segment with RWX permissions /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/riscv64-unknown-elf-objdump -S -C -d -l -x riscv_wrapper.elf > riscv_wrapper.dump /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/.conda-env/riscv-tools/bin/riscv64-unknown-elf-objcopy -O binary --change-addresses=-0x80000000 riscv_wrapper.elf riscv_wrapper.img /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/scripts/smartelf2hex.sh riscv_wrapper.elf > riscv_wrapper.hex /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/bin/vpp.pl /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/aesMacro/c_dispatch 1 1 testHistory.txt 0 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/aesMacro/aesMacro_sim_xrun.log 0 \""/mnt/data/cadtools/cds/xcelium/23.09.006/tools/bin/64bit/xrun -64bit -R -xmlibdirname /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d -afile /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli/v2c.tab -loadpli1 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -sv_lib /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -loadvpi /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d/run.d/librun.so:boot -log /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/aesMacro/aesMacro_sim_xrun.log"\" use_gdb flags = 0 WARNING: testInfo file testHistory.txt does not exit..Creating one.. From Parent PID=3510491 From Child PID=3510496 EXEC: /mnt/data/cadtools/cds/xcelium/23.09.006/tools/bin/64bit/xrun -64bit -R -xmlibdirname /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d -afile /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/pli/v2c.tab -loadpli1 /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -sv_lib /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/lib/libvpp.so -loadvpi /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/xcelium.d/run.d/librun.so:boot -log /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/aesMacro/aesMacro_sim_xrun.log Executing /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/testSuites/bareMetalTests/aesMacro/c_dispatch 0x45682399 TOOL: xrun(64) 23.09-s006: Started on Aug 19, 2024 at 17:42:20 EDT xrun(64): 23.09-s006: (c) Copyright 1995-2024 Cadence Design Systems, Inc. Loading snapshot worklib.cep_tb:sv .................... Done __exit = jtag_tick( | xmsim: *F,NOFDPI (/mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/generated-src/chipyard.harness.TestHarness.CEPRocketConfig/gen-collateral/SimJTAG.v,76|32): Function jtag_tick not found in any of the shared object specified with -SV_LIB switch.** The corresponding import DPI declaration is done in file /mnt/data/projects/avalon/jkrim/cep_v4_7_test_verilator/CEP/sims/cep_cosim/generated-src/chipyard.harness.TestHarness.CEPRocketConfig/gen-collateral/SimJTAG.v at line no. 6. TOOL: xrun(64) 23.09-s006: Exiting on Aug 19, 2024 at 17:42:21 EDT (total: 00:00:01)

jordankrim commented 2 months ago

I have solved this issue myself. Some Makefiles changed to add some files (no idea why they are not being comiled already) and other fixes and needed to have env var LD_PRELOAD set to point to a compiled version of the GCC GLIBCXX (14) library. In order to semi-automate the process, I have made a Perl script that changes all the files necessary on CEP v4.5 and v4.7 to be able to run Xcelium and Verilator on the bareMetal Tests.